This application is based upon and claims priority of Japanese Patent Application No. 2002-1675, filed in Jan. 8, 2002, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having conductive plugs for connecting a capacitor and a conductive pattern and a method of manufacturing the same.
2. Description of the Prior Art
The ferroelectric capacitor constituting the FeRAM (Ferroelectric Random Access Memory), which is currently mass-produced, has such a structure that wirings are connected onto both the lower electrode and the upper electrode, i.e., the planar structure. In the ferroelectric capacitor having the planar structure, the contact area of the lower electrode is shaped to protrude from the side of the ferroelectric film.
Corresponding to the requirements of the higher integration of the FeRAM, the capacitor having the stacked structure, which is able to reduce the memory cell area smaller, is being developed. The stacked structure is the structure in which the conductive plug is connected to the undersurface of the lower electrode of the ferroelectric capacitor.
Next, steps of forming the capacitor having the stacked structure is explained with reference to FIGS. 1A, 1B, and 1C.
First, steps required until the structure shown in FIG. 1A is obtained will be explained hereunder.
MOS transistors 102 are formed on a silicon substrate 101, and then a first interlayer insulating film 103 for covering the MOS transistors 102 is formed.
The MOS transistors 102 are formed on the silicon substrate 101 in a well region 105 that is surrounded by an element isolation layer 104. Each of the MOS transistors 102 has a gate electrode 102b formed on the silicon substrate 101 via a gate insulting film 102a, and impurity diffusion regions 102c serving as source/drain formed on both sides of the gate electrode 102b in the well region 105. Also, insulating sidewalls 106 used to form high concentration impurity regions 102d in the impurity diffusion regions 102c are formed on both side surfaces of the gate electrode 102b. 
First contact holes 103a are formed in the first interlayer insulating film 103 on one impurity diffusion regions 102c of the MOS transistors 102, and then a first contact plug 107 is buried in the first contact holes 103a respectively.
The material constituting the first contact plug 107 is the same as that constituting other contact plugs (not shown) that are not connected to the lower electrode of the capacitor. For example, in Patent Application Publication (KOKAI) 2001-44376, the contact plug connected to the lower electrode of the capacitor and the contact plug not connected to the lower electrode of the capacitor are formed of tungsten or polysilicon that is formed by the same step.
Then, a first metal film 108, a ferroelectric film 109, and a second metal film 110 are formed sequentially on the first contact plugs 107 and the first interlayer insulating film 103.
Then, as shown in FIG. 1B, the first metal film 108, the ferroelectric film 109, and the second metal film 110 are patterned by using a hard mask continually, so that the first metal film 108 is shaped into a lower electrode 108a of a capacitor 111, the ferroelectric film 109 is shaped into a ferroelectric film 109a of the capacitor 111, and the second metal film 110 is shaped into an upper electrode 110a of the capacitor 111. In this case, the capacitor 111 is the stacked-type capacitor, and the lower electrode 108a is connected to one impurity diffusion region 102c of the MOS transistor 102 via the underlying first contact plug 107.
Then, as shown in FIG. 1C, a capacitor protection film 112 is formed on the capacitors 111 and the first interlayer insulating film 103, and then a second interlayer insulating film 113 is formed on the capacitor protection film 112. Then, a second contact hole 113a is formed on the other impurity diffusion regions 102c of the MOS transistors 102 by patterning the second interlayer insulating film 113, the capacitor protection film 112 and the first interlayer insulating film 103 by virtue of the photolithography method. Then, a second contact plug 114 is formed in the second contact hole 113a. This second contact plug 114 is formed to connect the bit line (not shown), which is formed on the second contact plug 114, and the impurity diffusion regions 102c. 
Meanwhile, in many cases the FeRAM is mounted mixedly with the logic semiconductor device. As the embedded device in which the FeRAM and the logic circuit are mixed, there are the security associated chip which requires the authentication and the IC card employed in the local self-governing body.
In the logic semiconductor device, the tungsten plug is employed as the plug to connect the underlying conductive pattern and the overlying conductive pattern, and in addition the resistance value of the tungsten plug is employed as the spice parameter used to design the circuit.
Accordingly, in the sense to utilize the circuit design resource accumulated up to this time and reduce the developmental man-hour and cost, the logic-embedded FeRAM needs the tungsten plug.
By the way, various heat treatments such as the crystallizing annealing, the recovery annealing, or the like are needed in the oxygen containing atmosphere to form the ferroelectric capacitor. Typically the RTA (Rapid Thermal Annealing) process is carried out at 750xc2x0 C. for 60 seconds as the annealing for crystallizing the ferroelectric film. Also, after the formation of the capacitor, the film quality recovery annealing of the ferroelectric film is carried out in the furnace at 650xc2x0 C. for 60 minutes.
Here, as shown in FIGS. 1B and 1C, if the tungsten plug is employed as the first contact plugs 107 formed immediately under the lower electrodes 108a of the capacitors 111, the tungsten plug is oxidized at the very high speed and at the low temperature in the annealing process in the oxygen containing atmosphere.
When the tungsten plug starts to oxidize, such oxidation spreads over the entire plug. Thus, the contact failure of the lower electrode easily occurs, so that the reduction in yield of the FeRAM device is caused. Such oxidation of the tungsten plug is also set forth in Patent Application Publication (KOKAI) Hei 10-303398. In order to keep the normal contact by preventing the oxidation of the tungsten plug, the heating temperature in the annealing process of the capacitor must be lowered much more.
Therefore, the improvement in performance of the ferroelectric capacitor and the improvement in contact performance of the tungsten plug are in the trade-off relationship.
As described above, the second contact hole 113a for connecting the bit line and the impurity diffusion regions is opened after the capacitors 111 and the second interlayer insulating film 113 are formed. This is because, if the second contact hole for the bit line connection is formed in the first interlayer insulating film 103 simultaneously with the first contact hole 103a, the upper surface of the tungsten plug formed in the second contact hole is exposed after the formation of the capacitor and then oxidized.
However, the aspect ratio of the second contact hole 113a shown FIG. 1C is increased with the future miniaturization of the FeRAM. Thus, the etching technology for forming the second contact hole 113a, the formation of the glue layer acting as the underlying layer before the tungsten is buried in the second contact hole 113a, etc. should be improved.
It is an object of the present invention to provide a semiconductor device capable of improving a yield of a contact plug formed directly under the capacitor lower electrode and also facilitating the design of remaining contact plugs, and a method of manufacturing the same.
The above subject can be overcome by providing a semiconductor device which comprises first and second impurity diffusion regions constituting a transistor formed in a semiconductor substrate; a first insulating film formed over the semiconductor substrate; a first hole formed in the first insulating film above the first impurity diffusion region; a first conductive plug formed in the first hole and made of a metal film; a second hole formed in the first insulating film above the second impurity diffusion region; a second conductive plug formed on the second hole and made of conductive material that is hard to be oxidized rather than the metal film; and a capacitor consisting of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film formed of one of ferroelectric substance and high-dielectric substance, and an upper electrode.
Also, the above subject can be overcome by providing a semiconductor device manufacturing method which comprises the steps of forming a transistor having first and second impurity diffusion regions formed in a semiconductor substrate; forming a first insulating film, which covers the transistor, over the semiconductor substrate; forming a first hole in the first insulating film on the first impurity diffusion region; forming a first conductive plug made of a metal film in the first hole; forming a second conductive plug, which is made of conductive material that is hard to be oxidized rather than the metal film, in the first insulating film on the second impurity diffusion region; forming a first conductive film, a dielectric film made of any one of ferroelectric substance and high-dielectric substance, and a second conductive film sequentially on the second conductive plug and the first insulating film; and forming a capacitor on the second conductive plug by patterning the second conductive film, the dielectric film, and the first conductive film.
According to the present invention, the conductive material constituting the conductive plugs formed directly under the lower electrode of the capacitor is formed of the material that is less oxidized than the metal of the other conductive plug. For example, the conductive plug formed just under the capacitor is made of any one of doped silicon and oxide conductive material, and also other conductive plugs are formed of a film that contains the tungsten.
In the situation that the conductive film serving as the lower electrode of the capacitor is formed on the conductive plug that is made of doped silicon or oxide conductive material, the conductive plug formed directly under the capacitor is difficult to be oxidized by the annealing in the oxygen containing atmosphere. Thus, the conductive plug makes good connection between the capacitor and the impurity diffusion region, and improves the yield of the device.
Also, other conductive plugs not formed just under the capacitor are formed of the metal film, which has the smaller electric resistance than the doped silicon or the oxide conductive material, to consider preferentially the reduction in the electric resistance. Therefore, the conventional design rule can be applied to the logic circuit and the bit signal.
In this case, when the crystallization annealing of the ferroelectric film constituting the capacitor or the oxygen annealing after the formation of the capacitor is carried out, the conductive plugs not formed just under the capacitor can be prevented from being oxidized by covering the conductive plugs with the oxidation preventing film.